1. Field of the Invention
The present invention relates to a memory device and, more particularly, to a ferroelectric memory device method thereof.
2. Background of the Related Art
A ferroelectric random access memory (FRAM) has the data processing speed as fast as a DRAM, which is widely used as a semiconductor memory device, and stores data even in a power-off state. The FRAM has a structure similar to the DRAM and employs ferroelectric as the capacitor material to use its high residual polarization characteristic. With this characteristic, the data stored in the FRAM is not erased even when electric field applied thereto is removed.
As shown in FIG. 1, a polarization induced by electric field does not disappear, even when the electric field is removed, due to existence of spontaneous polarization but remains in a specific amount (states of d and a). The states d and a correspond to data 1 and 0, respectively, for the memory device.
FIG. 2 illustrates the configuration of the unit cell of a conventional ferroelectric memory device. FIG. 3 illustrates the configuration of the cell array of the conventional ferroelectric memory device. FIG. 4 illustrates operation waveforms of the conventional ferroelectric memory device.
An ideal structure of an FRAM using a ferroelectric layer is the one which is similar to DRAM. However, it has the problem in terms or integration, which is difficult to solve if new materials for forming an electrode and barrier are not used. Such problems occur because capacitors cannot be directly formed on a silicon substrate or polysilicon layer to make the area of FRAM larger than the DRAM with the same capacitance. Furthermore, when electric field is repeatedly applied to the ferroelectric to reiterate polarization inversion, the amount of residual polarization is reduced, which results in fatigue of the thin film. Such a fatigue deteriorates the reliability of device.
The FRAM structure shown in FIG. 2 has been used with regard to such matters, including substitutes for electrode materials currently developed, integration, stability or ferroelectric thin film and operation reliability. The unit cell of the conventional FRAM consists of first and second NMOS transistors 1 and 3 whose gates are commonly connected to a word line 5, and first and second ferroelectric capacitors 2 and 4 formed using a ferroelectric material. The drain and source of the first transistor 1 are respectively connected to a bit line (Bit_n) 6 and a first node 1 (N1). The drain and source of the second transistor 3 are respectively connected to a/bit line (BitB_n) 7 and a second node 2 (N2). The electrodes of the first ferroelectric capacitor 2 are connected to the first node 1 (N1) and a cell plate line 8, and the electrodes of the second ferroelectric capacitor 4 are connected to the second node 2 (N2) and the cell plate line 8.
The unit cell of the conventional FRAM forms the cell array of FIG. 3. The word lines and plate lines are arranged in parallel in the direction of the row, and the bit lines and/bit lines are arranged in parallel in the direction of the column. Each memory cell is located at the point where each row and each column intersect each other. Access to each memory cell can be performed by selecting both the row and column on which the memory cell is placed.
The operation of the conventional FRAM is described with reference to FIG. 4. A chip enable signal CSBpad is enabled from a level xe2x80x9cHIGHxe2x80x9d to a level xe2x80x9cLOWxe2x80x9d, to start decoding of the address signal. A word line driving signal applied to a selected word line transit from a level xe2x80x9cLOWxe2x80x9d to a level xe2x80x9cHIGHxe2x80x9d to select a cell. Before the word lines are activated to allow memory cell data to be loaded on corresponding bit line and/bit line, the bit line and/bit line become an equivalent potential of VSS according to a control signal EQ for the equivalent potential.
Thereafter, the word line driving signal is enabled from a level xe2x80x9cLOWxe2x80x9d to level xe2x80x9cHIGHxe2x80x9d, to electrically connect the selected memory cell to the bit line and/bit line. Upon connection of the selected memory cell to the bit line and/bit line, a pulse of a level xe2x80x9cHIGHxe2x80x9d is applied to the plate line P/L, to load the data stored in the ferroelectric capacitor on bit line and/bit line. In this state, a sense amplifier enable signal SAN (for turning on the NMOS transistor of a sense amplifier) transits from a level xe2x80x9cLOWxe2x80x9d to a level xe2x80x9cHIGHxe2x80x9d, and a sense amplifier enable signal SAP (for turning on the PMOS transistor of the sense amplifier) transits from a level xe2x80x9cHIGHxe2x80x9d to a level xe2x80x9cLOWxe2x80x9d, such that the voltage of the bit line and/bit line is amplified.
To recover the data destroyed during data reading operation, the signal CSBpad is transferred from a level xe2x80x9cHIGHxe2x80x9d to a level xe2x80x9cLOWxe2x80x9d, being disabled while the word lines is being activated. The signal CSBpad is disabled from a level xe2x80x9cHIGHxe2x80x9d to a level xe2x80x9cLOWxe2x80x9d and the signal applied to the plate line is transferred from a level xe2x80x9cHIGHxe2x80x9d to a level xe2x80x9cLOWxe2x80x9d, to restore the data destroyed.
In the conventional FRAM, as described above, the word line and the plate line are separately constructed, to complicate the structure of the memory cell, which increases its area. Thus, the word line and plate line receive control signals different from each other, which creates difficulty in the control of the control signals in the input/output operation of data.
Accordingly, the present invention is directed to a ferroelectric memory device that substantially obviates at least the problems and disadvantages of the related art.
An object of the present invention is to provide a nonvolatile ferroelectric memory device designed with an effective layout.
A further object of the invention is to eliminate a separate cell plate line.
To accomplish the object of the present invention, there is provided a nonvolatile ferroelectric memory device, including: first and second split word lines formed over first and second active regions of a semiconductor substrate, isolated from each other, the first and second split word lines being arranged in the first direction; source and drain regions formed in the first active region placed on both side of the first split word line and the second active region placed on both sides of the second split word line; a conductive barrier layer, a first capacitor electrode and a ferroelectric layer, sequentially formed on the first and second split word lines; two second capacitor electrodes one of which is connected to one of the source and drain regions of the second active region and formed over the first split word line, the other one being connected to one of the source and drain regions of the first active region and formed over the second split word line; and first and second bit lines arranged perpendicular to the first and second split word lines in the second direction, the first bit line being connected to the other one of the source and drain regions of the first active region, the second bit line being connected to the other one of the source and drain regions of the second active region.
To accomplish another object of the invention a method of fabricating a nonvolatile ferroelectric memory device, comprising the steps of: sequentially forming a gate oxide layer, polysilicon layer for forming gates and word lines, conductive barrier layer and first capacitor electrode layer on a semiconductor substrate having first and second active regions isolated from each other by an isolation layer; selectively etching the stacked layers, to form first and second split word lines across the first and second active regions; forming source and drain regions in exposed portions of the first and second active regions using the first and second split word lines as a mask, and sequentially forming a first oxide layer and planarizing insulation layer on the overall surface of the substrate; improving viscosity of the planarizing insulation layer through heat treatment, removing the planarizing insulation layer by a predetermined thickness using etchback process, to expose the first capacitor electrode, and forming a ferroelectric layer and second capacitor electrode layer on the overall surface of the substrate; patterning the second capacitor electrode layer and forming a second oxide layer on the overall surface of the substrate; forming contact holes to expose the drain regions of the first and second active regions, forming a contact plug which comes into contact with the drain region of the first active region and second capacitor electrode layer placed over the second split word line through one of the contact hole, and forming another contact plug which comes into contact with the drain region of the second active region and second capacitor electrode layer placed over the first split word line through the other contact hole; and forming a third oxide layer on the overall surface of the substrate including the contact plug, forming contact holes to expose the source regions of the first and second active regions, and forming first and second bit lines perpendicular to the first and second split word lines, the first and second bit lines coming into contact with the source regions through the contact holes.
The first split word line and first capacitor electrode, placed over the first split word line, are connected to each other at a predetermined portion of a peripheral circuit region, and the second split word line and first capacitor electrode, placed over the second split word line, are connected to each other at a predetermined portion of the peripheral circuit region. The first and second capacitor electrodes are formed of a metal such as Pt. The planarizing insulation layer for filling the space between the first and second split word lines is formed of SOG or BPSG. The heat treatment is carried out to the planarizing insulation layer at a temperature of 800 to 900xc2x0 C., to shrink its volume by 20 to 30%, improving its viscosity. The contact plugs are formed in such a manner that portions of the second oxide layer, ferroelectric layer, planarizing insulation layer and first oxide layer, placed on the drain regions of the first and second active regions, are selectively removed, to form the contact holes, simultaneously, to expose a portion of the second capacitor electrode, and a material for forming the contact plugs is deposited to completely fill the contact holes and patterned so as to come into contact with the drain regions and second capacitor electrode.
The contact holes for exposing the source regions of the first and second active regions are formed in such a manner that the third oxide layer is formed on the overall surface of the substrate including the contact plugs, and portions of the third oxide layer, second oxide layer, ferroelectric layer, planarizing insulation layer and first oxide layer, placed on the source regions, are selectively removed.
The object of the present invention can be achieved in a whole or in parts by a method of fabricating a nonvolatile ferroelectric memory device, comprising the steps of: sequentially forming a gate oxide layer, polysilicon layer for forming gates and word lines, conductive barrier layer and first capacitor electrode layer on a semiconductor substrate having first and second active regions isolated from each other by an isolation layer; selectively etching the stacked layers, to form first and second split word lines across the first and second active regions; forming source and drain regions in exposed portions of the first and second active regions using the first and second split word lines as a mask, and sequentially forming a first oxide layer and photoresist layer on the overall surface of the substrate; removing the photoresist layer, filled between the first and second split word lines, by a predetermined thickness using etchback, removing the first oxide layer to expose the first capacitor electrode, and completely removing remaining photoresist layer; forming a ferroelectric layer and second capacitor electrode layer on the overall surface of the substrate including the exposed first capacitor electrode, patterning the second capacitor electrode layer, and forming a second oxide layer on the overall surface of the substrate; forming contact holes to expose the drain regions or the first and second active regions, forming a conductive connection layer which connects the drain region of the first active region to the second capacitor electrode placed over the second split word line through one of the contact hole, and forming another conductive connection layer which connects the drain region of the second active region to the second capacitor electrode placed over the first split word line through the other contact hole; and forming a third oxide layer on the overall surface of the substrate including the conductive connection layer to bury the space between the first and second split word lines, forming contact holes to expose the source regions of the first and second active regions, and forming first and second bit lines perpendicular to the first and second split word lines, the first and second bit lines coming into contact with the source regions through the contact holes.
The objects of the present invention can be achieved in a whole or in parts by a nonvolatile ferroelectric memory device, comprising: first and second split word lines parallel with each other; first and second shunt split word lines branched from the first and second split word lines respectively; a first transistor whose gate is connected to the first split word line; a second transistor whose gate is connected to the second split word line; a bit line connected to one electrode of the first transistor and arranged perpendicular to the first and second split word lines; a bit line connected to one electrode of the second transistor, arranged parallel with the bit line and perpendicular to the first and second split word lines; a first ferroelectric capacitor, one electrode of the first ferroelectric capacitor being connected to the other electrode of the first transistor, the other electrode of the first ferroelectric capacitor being connected to the second shunt split word line; and a second ferroelectric capacitor, one electrode of the second ferroelectric capacitor being connected to the other electrode of the second transistor, the other electrode of the second ferroelectric capacitor being connected to the first shunt split word line.
The objects of the present invention can be achieved in a whole or in parts by a nonvolatile ferroelectric memory device, comprising: first and second split word lines formed over first and second active regions of a semiconductor substrate, isolated from each other, the first and second split word lines being arranged in the first direction; source and drain regions formed in the first active region placed on both sides of the first split word line and second active region placed on both sides of the second split word line; first and second bit lines isolated from neighboring layers and arranged perpendicular to the first and second split word lines in the second direction, the first bit line being connected to one of the source and drain regions of the first active region, the second bit line being connected to one of the source and drain regions of the second active region; two first capacitor electrodes formed over the first and second split word lines in a cylindrical shape with the bottom and cylinder, one of the first capacitor electrodes being connected to the other one of the source and drain regions of the first active region, the other one of the first capacitor electrodes being connected to the other one of the source and drain regions of the active region, a ferroelectric layer formed on the inner walls of the first capacitor electrodes; second capacitor electrodes filled in the first capacitor electrodes; and a first shunt split word line formed over the first split word line and connected to the second capacitor electrode of the second active region, and second shunt split word line formed over the second split word line and connected to the second capacitor electrode of the first active region.
When it is assumed that the semiconductor substrate is divided into rectangular blocks with longer and shorter sides, and among neighboring four blocks placed at a certain region, the first, second, third and fourth clockwise are respectively called a block A, block B, block A and block B, and this four-block structure is repeated in the substrate, the first active region is formed over one blocks A and the other block A, arranged adjacent in diagonal direction, and the second active region is formed over one block B horizontally located next to the block A, and the other block B vertically located next to the block A, the two blocks Bs being arranged in diagonal direction. The first direction is perpendicular to the longer sides of the blocks A and B, and second direction is parallel with the longer sides of the blocks A and B. Each first capacitor electrode connected to one of the source and drain regions of each of the first and second active regions has a flat shape, not having the cylindrical portion.
The objects of the present invention can be achieved in a whole or in parts by a method of fabricating a nonvolatile ferroelectric memory device, comprising the steps of: forming a gate oxide layer and polysilicon layer for forming gates and word lines on a semiconductor substrate having first and second active regions isolated from each other by an isolation layer, and selectively etching them, forming first and second split word lines across the first and second active regions; forming source and drain regions in exposed portions of the active regions using the first and second split word lines as a mask, and forming a first interlevel insulating layer on the overall surface of the substrate; forming bit line contact holes to expose the source regions of the first and second active regions, and forming first and second bit lines perpendicular to the first and second split word lines, coming into contact with the source regions through the bit line contact holes; forming a second interlevel insulating layer, forming contact holes to expose the drain regions of the first and second active regions, forming first capacitor electrodes in a cylindrical shape, coming into contact with the drain regions through the contact holes; forming a ferroelectric layer on the overall surface of the substrate on which the first capacitor electrodes are formed, and forming second capacitor electrodes to be filled in the cylinders of the first capacitor electrodes; and forming a third interlevel insulating layer on the overall surface of the substrate including the second capacitor electrodes, forming contact holes to expose portions of the second capacitor electrodes, forming a metal layer on the overall surface of the substrate and selectively etching it, to form first and second shunt split word lines.
Before the third interlevel insulating layer is formed, portions of second capacitor electrodes, ferroelectric layer and first capacitor electrodes in the cylindrical shape are removed by a predetermined thickness by CMP process, isolating capacitors by the unit cell. A process of forming the first capacitor electrodes comprises the steps of: selectively removing the second interlevel insulating layer, first and second bit lines, placed on the drain regions, to form capacitor contact holes; forming a conductive layer and interlevel insulating layer on the overall surface of the substrate including the capacitor contact holes, and patterning them to be left only on regions where capacitors will be formed; and forming another conductive layer on the overall surface of the substrate including the patterned interlevel insulating layer, and etching back it, to be left on the sides of the patterned interlevel insulating layer in the form of sidewall.
The first shunt split word line and first split word line come into contact with each other at a predetermined point of a peripheral circuit region around a cell array, to receive the same signal, and the second shunt split word line and second split word line come into contact with each other at a predetermined point of the peripheral circuit region around the cell array, to receive the same signal. Each first capacitor electrode connected to the drain region of each of the first and second active regions has a flat shape, not having the cylindrical portion.
The objects of the present invention can be achieved in a whole or in parts by a nonvolatile ferroelectric memory device, comprising: first and second split word lines parallel with each other; first and second shunt split word lines branched from the first and second split word lines respectively; a first transistor whose gate is connected to the first split word line; a second transistor whose gate is connected to the second split word line; a bit line connected to one electrode of the first transistor and arranged perpendicular to the first and second split word lines; a bit line connected to one electrode of the second transistor, arranged parallel with the bit line and perpendicular to the first and second split word lines; a first lower ferroelectric capacitor one electrode of the first lower ferroelectric capacitor being connected to the other electrode of the first transistor, the other electrode of the first lower ferroelectric capacitor being connected to the second split word line; a first upper ferroelectric capacitor, one electrode of the first upper ferroelectric capacitor being connected to the other electrode of the first transistor, the other electrode of the first upper ferroelectric capacitor being connected to the second shunt split word line; a second lower ferroelectric capacitor, one electrode of the second lower ferroelectric capacitor being connected to the other electrode of the second transistor, the other electrode of the second lower ferroelectric capacitor being connected to the first split word line; and a second upper ferroelectric capacitor, one electrode of the second upper ferroelectric capacitor being connected to the other electrode of the second transistor, the other electrode of the second upper ferroelectric capacitor being connected to the first shunt split word line.
The present invention can be achieved in a whole or in parts by a nonvolatile ferroelectric memory device, comprising: first and second split word lines formed over first and second active regions of a semiconductor substrate, isolated from each other, the first and second split word lines being arranged in the first direction; source and drain regions formed in the first active region placed on both sides of the first split word line and second active region placed on both sides of the second split word line; a conductive barrier layer, first capacitor electrode layer and first ferroelectric layer sequentially formed on the first and second split word lines; a second capacitor electrode formed over the first split word line and connected to one of the source and drain regions of the second active region, and another second capacitor electrode formed over the second split word line and connected to one of the source and drain regions of the first active region; a second ferroelectric layer formed on the second capacitor electrodes; a first shunt split word line formed over the first split word line and connected to the second capacitor electrode on the second active region, and second shunt split word line formed over the second split word line and connected to the second capacitor electrode on the first active region; and first and second bit lines arranged perpendicular to the first and second split word lines, the first bit line being connected to one of the source and drain regions of the first active region, the second bit line being connected to one of the source and drain regions of the second active region.
The present invention can be achieved in a whole or in parts by a method of fabricating a nonvolatile ferroelectric memory device, comprising the steps of: sequentially forming a gate oxide layer, polysilicon layer for forming gates and word lines, conductive barrier layer and first capacitor electrode layer on a semiconductor substrate having first and second active regions isolated from each other by an isolation layer; selectively etching the stacked layers, to form first and second split word lines across the first and second active regions; forming source and drain regions in exposed portions of the first and second active regions using the first and second split word lines as a mask, and sequentially forming, a first oxide layer and planarizing insulation layer on the overall surface of the substrate; improving viscosity of the planarizing insulation layer through heat treatment, removing the planarizing insulation layer by a predetermined thickness using etchback process, to expose the first capacitor electrode 95, and forming a first ferroelectric layer and second capacitor electrode layer on the overall surface of the substrate; patterning the second capacitor electrode layer and forming a second oxide layer on the overall surface of the substrate; forming contact holes to expose the drain regions of the first and second active regions, forming a contact plug which comes into contact with the drain region of the first active region and second capacitor electrode layer placed over the second split word line through one of the contact hole, and forming another contact plug which comes into contact with the drain region of the second active region and second capacitor electrode layer placed over the first split word line through the other contact hole; forming a second ferroelectric layer on the overall surface of the substrate including the contact plug, forming a first shunt split word line over the first split word line, being connected to the second capacitor electrode on the second active region, and forming a second shunt split word line over the second split word line, being connected to the second capacitor electrode on the first active region; and forming a third oxide layer on the overall surface of the substrate, forming contact holes to expose the source regions of the first and second active regions, and forming first and second bit lines perpendicular to the first and second split word lines, the first and second bit lines coming into contact with the source regions through the contact holes.
The first split word line, first capacitor electrode, placed over the first split word line, and first shunt split word line are connected to one another at a predetermined portion of a peripheral circuit region, and the second split word line, first capacitor electrode, placed over the second split word line, and second shunt split word line are connected to one another at a predetermined portion of the peripheral circuit region.
The planarizing insulation layer for filling the space between the first and second split word lines is formed of SOG or BPSG. The heat treatment is carried out to the planarizing insulation layer at a temperature of 800 to 900xc2x0 C., to shrink its volume by 20 to 30%, improving its viscosity.
The contact plugs are formed in such a manner that portions of the second oxide layer, ferroelectric layer, planarizing insulation layer and first oxide layer, placed on the drain regions of the first and second active regions, are selectively removed, to form the contact holes, simultaneously, to expose a portion of the second capacitor electrode, and a material for forming the contact plugs is deposited to completely fill the contact holes and patterned so as to come into contact with the drain regions and second capacitor electrode. The contact holes for exposing the source regions of the first and second active regions are formed in such a manner that the third oxide layer is formed on the overall surface of the substrate including the contact plugs, and portions of the third oxide layer, second oxide layer, second ferroelectric layer, first ferroelectric layer, planarizing, insulation layer and first oxide layer, placed on the source regions, are selectively removed.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.